1. Field of the Invention
The present invention generally relates to the field of semiconductor fabrication. More particularly, the present invention relates to a method and apparatus for forming edge metal to interconnect features in a semiconductor device.
2. Art Background
Lithography processes are typically used for semiconductor fabrication. A typical lithography process for forming two metal lines is illustrated in FIGS. 1a-1d. FIG. 1a shows a metal layer 12 deposited over a substrate 10. As illustrated in FIG. 1b, a positive photoresist 14 is then deposited over metal layer 12 and is exposed to radiation 18 through mask 16. Mask 16 has opaque features 22 and clear features 20.
Radiation 18 serves to render soluble in a suitable developer that portion of photoresist 14 exposed to radiation 18 through clear features 20. That portion of photoresist 14 that has not been exposed to radiation remains relatively insoluble in the developer. Photoresist layer 14 may then be developed in a suitable developer to form features 24 as illustrated in FIG. 1c. Metal layer 12 may then be subjected to a suitable metal etch that removes portions of metal layer 12 not covered by features 24. Features 24 may then be suitably removed leaving metal lines 26 and 28 as illustrated in FIG. 1d.
FIG. 2 shows a top view of metal lines 26 and 28. As illustrated in FIG. 2, metal line 26 interconnects two contacts 30 and 31 that may be formed in substrate 10 of FIG. 1a. Contacts 30 and 31 may also be referred to as "nails" or "plugs." Similarly, metal line 28 interconnects two contacts 32 and 33 that may be formed in substrate 10 of FIG. 1a.
The typical lithography process illustrated in FIGS. 1a-1d limits the size and density with which semiconductor devices may be fabricated. For example, the minimum resolution capability of the lithography process determines the minimum pitch 27 for metal lines 26 and 28. The pitch may be twice the width of one of the metal lines. For example, if a metal line is 0.5 .mu.m wide, then the pitch is 1.0 .mu.m. As illustrated in FIG. 2, the spacing between contacts 30 and 32, and between contacts 31 and 33, is also limited by the pitch of metal lines 26 and 28.
The pitch may depend on the lens used in exposing the photoresist to radiation through mask 16. The pitch may also depend on the equipment used to form metal lines 26 and 28. Typically, a machine (e.g., a stepper) that is capable of producing a pitch 27 for metal lines 26 and 28 of approximately 1.1 .mu.m (micrometers or microns), costs approximately three times as much as a machine capable of producing a pitch of approximately 1.8 .mu.m, and approximately 30 times as much as a machine capable of producing a pitch of approximately 2.2 .mu.m. Therefore, the cost of purchasing equipment to manufacture metal lines having a small pitch can be extremely expensive. Therefore, what is needed is a method of forming metal lines having a reduced pitch using existing or older machines without the need to purchase more expensive newer equipment. Also what is needed is the ability to form smaller pitches than what is possible using existing fabrication equipment and the conventional lithography process illustrated in FIGS. 1a-1d. Additionally, what is needed is the ability to form smaller metal lines having smaller pitches to that the density of metal lines formed on a semiconductor substrate is increased relative to conventional lithography processes.
Given that fabrication densities are limited by the pitch of metal lines, semiconductor device manufacturers have increasingly gravitated to forming multiple layers of metal lines or interconnect to reduce the area of the silicon substrate used to build a device. Each layer of interconnect is still limited by the pitch between metal lines, but more features can be stacked onto a piece of silicon by using multiple layers of interconnect than is possible if only a single layer of metal or interconnect was employed to interconnect features of a device. Typical memory cells (e.g., SRAM cells) may use one layer of local interconnect formed from titanium (Ti), a mixture of Ti and tungsten, or other conductive material, and multiple layers of metal lines formed from aluminum (Al), copper (Cu), or other metal.
A typical process for cross-coupling pairs of contacts using multiple layers of interconnect is illustrated in FIGS. 3a-3d. FIG. 3a shows four contacts 40-43 which may be formed in an oxide layer (not shown). A first layer of metal or a local interconnect layer is deposited over contacts 40-43, exposed to a metal mask and etched to form metal line 46 interconnecting contacts 41 and 43 as illustrated in FIG. 3b. An interlayer dielectric 48 (e.g., SiO.sub.2) is formed over contacts 40-43 and metal line 46 as illustrated in FIG. 3c. Interlayer dielectric 48 may then be planarized as known in the art. Openings 50 and 52 may then be formed in interlayer dielectric 48 using a contact mask and etch. As illustrated in FIG. 3c, openings 50 and 52 provide a via to contacts 40 and 42. A second layer of metal may then be deposited over contacts 40-43, inter-layer dielectric 48 and openings 50 and 52. The second layer of metal may then be exposed to another metal mask and etched to form metal line 54 interconnecting contacts 40 and 42 as illustrated in FIG. 3d. Another inter-layer dielectric (not shown) would then be formed over contacts 40-43 and metal lines 46 and 54, and planarized. To further interconnect contacts 40-43 to other contacts or features elsewhere in the semiconductor device, another contact mask and etch would be required to form an opening to the appropriate contact(s), and another layer of metal would then be deposited, exposed to a third metal mask, and etched to form the interconnection.
As illustrated in FIGS. 3a-3d, forming a semiconductor device using multiple layers greatly increases the amount of time required to manufacture a device, the probability of quality and reliability problems, the cost of materials to form the device since more materials are used, and the cost of manufacturing the device. Therefore, what is needed is a method to reduce the number of process steps, the number of layers of interconnect and/or metal lines required in a semiconductor device, the cost and time of manufacturing a semiconductor device, and the quality and reliability problems associated with constructing a device from multiple layers of interconnect. Furthermore, what is needed is a method of fabricating a semiconductor device using a reduced number of interconnect layers without substantially increasing the size of the device.
Previous metal lines that have been formed along an edge or sidewall of a feature have been considered to be defects or undesirable features. For example, an MSD process for achieving low sheet resistance of a source/drain local interconnect is described by Uehara et al. in A NOVEL LOCAL INTERCONNECT TECHNOLOGY (MSD) FOR HIGH-PERFORMANCE LOGIC LSIS WITH EMBEDDED SRAM (1996 Symposium on VLSI Technology, pp 142-143, published by IEEE, Piscataway, N.J. (1996)). FIG. 3(b) of Uehara et al. discloses that MSD without a mask may form separate source/drain local interconnect next to sidewall spacers when the gate electrode distance is greater than approximately 0.8 .mu.m. However, Uehara et al. did not test an MSD structure where the gate electrode distance was greater than 0.6 .mu.m apparently due to concerns about forming a source/drain local interconnect having an extremely high sheet resistance (e.g., an open circuit).
In conventional etching technology, undesirable metal "stringers" may be formed between metal lines as a result of incomplete etching. For example, FIG. 20a shows a cross-sectional view of a metal layer 2004 disposed over substrate 2000 and feature 2002 having sidewall 2003. Metal layer 2004 may be patterned (e.g., metal mask plus isotropic etch) to form metal lines 2006 and 2008 as shown in FIG. 20b. If the patterning does not completely remove the metal layer next to sidewall 2003, then a metal stringer 2008 may remain next to sidewall 2003. The metal stringer is an undesirable structure that may short metal lines 2006 and 2008. Processes are generally designed so that the metal etch sufficiently eliminates metal stringers.